Please refer to FIG. 1 which is a schematic diagram illustrating the transmission among a plurality of master devices 111, 112, . . . , 11n and a plurality of target devices 121, 122, . . . , 12n via a shared bus 10. In order to coordinate the data transmission, an arbiter 13 is provided between the master devices 111, 112, . . . , 11n and the shared bus 10 to arbitrate the bus grant to which of the master devices in a certain period. Generally, a fixed priority or a Round-Robin mechanism is employed for the arbitration of the shared bus architecture.
In order to increase the utility rate of the shared bus 10, a retry mechanism is also widely applied to the current bus protocol, e.g. a peripheral component interconnect (PCI) bus protocol. That is, when the dominating one of the master devices, for example the master device 111, outputs a data transfer request signal to the target device 121 but the target device 121 cannot achieve the data transaction at that time, the target device 121 will output a retry signal to the master device 111. In response to the retry signal, the arbiter 13 will rearrange the bus grant order. In other words, the master device 111 has to wait a certain period of time to become a candidate for the bus grant again. When it is the turn again of the master device 111 to dominate the shared bus 10, a data transfer request signal is re-outputted to the target device 121. By this way, the shared bus 10 will not be idly occupied by the incomplete data transaction between the master device 111 and the target device 121.
A conventional retry mechanism for use with a PCI bus is illustrated hereinafter with reference to FIG. 2. During the data transaction between the master device 111 and the target device 121, the master device 111, first of all, obtains the bus grant from the arbiter 13 and then sends out a FRAME# signal and an IRDY# signal to inform the target device 121 that it is ready for the data transaction. If the target device 121 is also ready for the data transaction, the target device 121 will send out a TRDY# signal and then the master device 111 starts the data transaction. Otherwise, the target device 121 will output a STOP# signal to stop the data transaction. The above situation is a typical retry mechanism since no data transaction has been completed between the master device 111 and the target device 121.
So far, the arbiter coordinates the bus grant only depending on the request signals from the master devices. The application of the retry mechanism, under this circumstance, possibly causes the “starve” of the master device. For example, for some bus configurations or in a long-term operation, it possibly occurs that one of the master devices cannot complete the data transaction all the time since the target device happens to be busy whenever the master device gets the bus grant. Accordingly, the transaction cannot be achieved for a long time so as to “starve” the master device.
Therefore, the purpose of the present invention is to develop an arbitrating method and device for coordinating the bus grant to deal with the above situations encountered in the prior art.